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CS5166
CS5166
5-Bit Synchronous CPU Controller with Power-Good and Current Limit
Description
The CS5166 is a synchronous dual NFET Buck Regulator Controller. It is designed to power the core logic of the latest high performance CPUs. It uses the V2TM control method to achieve the fastest possible transient response and best overall regulation. It incorporates many additional features required to ensure the proper operation and protection of the CPU and power system. The CS5166 provides the industry's most highly integrated solution, minimizing external component count, total solution size, and cost. The CS5166 is specifically designed to power Intel's Pentium(R) II processor and includes the following features: 5-bit DAC with 1% tolerance, Power-Good output, adjustable hiccup mode over-current protection, VCC monitor, Soft Start, adaptive voltage positioning, over-voltage protection, remote sense and current sharing capability. The CS5166 will operate over a 4.15 to 14V range and is available in a 16 lead wide body surface mount package.
Features
s V2TM Control Topology s Dual N-Channel Design s 125ns Controller Transient Response s Excess of 1Mhz Operation s 5-bit DAC with 1% Tolerance s Power-Good Output with Internal Delay s Adjustable Hiccup Mode Over Current Protection s Complete Pentium(R)II System Requires just 21 Components s 5V and 12V Operation s Adaptive Voltage Positioning s Remote Sense Capability s Current Sharing Capability
Application Diagram
5V to 2.8V @ 14.2A for 300MHz Pentium(R) II
5V 12V
1200F/10V x 3
s VCC Monitor s Overvoltage Protection (OVP) s Programmable Soft Start s 200ns PWM Blanking s 65ns FET Non-Overlap s 40ns Gate Rise and Fall Times (3.3nF load)
1200F 10V x 5
1F COFF 330pF 0.1F 0.1F
SS
COMP
VCC
GATE(H)
1.2H
3.0m 510
ISENSE
CS5166
0.1F
GATE(L)
VID0 VID1 VID2 VID3
VID4
PWRGD VFB PGnd LGnd
Pentium(R) II System
PWRGD
Package Options
16 Lead SO WIDE
VID0 VID1
1
VFB COMP LGnd PWRGD GATE(L) PGnd GATE(H) VCC
3.3K
VID4
1000pF
VID3 VID2
VID1
VID2 VID3
SS
VID0
VID4
COFF
is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel Corporation. V2
ISENSE
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 6/28/99
1
A
(R)
Company
CS5166
Absolute Maximum Ratings Operating Junction Temperature, TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 150C Lead Temperature Soldering: Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Sec max. above 183C, 230C Peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C
Pin Symbol Pin Name
VMAX 16V 6V 6V 6V 6V 6V 16V 16V 6V 6V 0V 0V
VMIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V 0V 0V
ISOURCE N/A 200A 10mA 1mA 1mA 1mA 1.5A Peak 200mA DC 1.5A Peak 200mA DC 1mA 10A 1.5A Peak 200mA DC 100mA
ISINK 1.5A Peak 200mA DC 10A 1mA 1mA 50mA 10A 1.5A Peak 200mA DC 1.5A Peak 200mA DC 1mA 30mA N/A N/A
VCC SS COMP VFB COFF VID0-4 GATE(H) GATE(L) ISENSE PWRGD PGnd LGnd
IC Power Input Soft Start Capacitor Compensation Capacitor Voltage Feedback and Current Sense Comparator Input Off-Time Capacitor Voltage ID DAC Inputs High-Side FET Driver Low-Side FET Driver Current Sense Comparator Input Power-Good Output Power Ground Logic Ground
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
1,2,3,4,6
VIDO - VID4
Voltage ID DAC inputs. These pins are internally pulled up to 5V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125V to 3.525V with 100mV increments. When VID4 is low (logic zero), the Error amp reference voltage is 1.325V to 2.075V with 50mV increments. Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and fault timing. Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the normal and extended off time. Current Sense Comparator Inverting Input Input Power Supply Pin. High Side Switch FET driver pin. High Current ground for the GATE(H) and GATE(L) pins. Low Side Synchronous FET driver pin. Power-Good Output. Open collector output drives low when VFB is out of regulation. Reference ground. All control circuits are referenced to this pin. Error Amp output. PWM Comparator reference input. A capacitor to LGnd provides Error Amp compensation. Error Amp, PWM Comparator feedback input, Current Sense Comparator Non-Inverting input, and PWRGD comparator input.
5 7 8 9 10 11 12 13 14 15 16
SS COFF ISENSE VCC GATE(H) PGnd GATE(L) PWRGD LGnd COMP VFB
2
CS5166
Electrical Characteristics: 0C < TA < 70C; 0C < TJ < 125C; 8V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1F; Unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s VCC Supply Current Operating 1VGATE > 1.6V GATE(H)<2V, GATE(L)>2V GATE(L)<2V, GATE(H)>2V Resistance to PGnd (Note 1) 30 30 20 1.2 1.0 40 40 65 65 50 2.0 1.5 80 80 100 100 115 V V ns ns ns ns k VFB = 0V COMP = 1.2V to 3.6V; VFB = 1.9V VFB = 1.9V, Adjust COMP voltage for Comp current = 60A COMP = 0V VCOMP=1.2V; VFB=2.2V; VSS > 2.5V Note 1 Note 1 Note 1 0.4 180 50 0.5 60 1.0 400 60 2 85 1.6 800 mA A dB MHz dB 15 0.85 0.1 30 1.0 1.0 60 1.15 A A V GATE(H) Switching GATE(H) not switching Start - Stop 3.75 3.65 3.95 3.87 80 4.15 4.05 V V mV 12 20 mA
3
CS5166
Electrical Characteristics: 0C < TA < 70C; 0C < TJ < 125C; 8V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1F; Unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Fault Protection continued SS Comp Clamp Voltage VFB Low Comparator s PWM Comparator Transient Response
VFB = 2.7V, VSS = 0V Increase VFB till normal off-time
0.50 0.9
0.95 1.0
1.10 1.1
V V
VFB = 1.2V to 5V 500ns after GATE(H) (after Blanking time) to GATE(H) = (VCC - 1V) to 1V
115
175
ns
Minimum Pulse Width (Blanking Time)
Drive VFB 1.2V to 5V upon GATE(H) rising edge (> VCC - 1V), measure GATE(H) pulse width
100
200
300
ns
s COFF Normal Off-Time Extended Off-Time s Time-Out Timer Time-Out Time Fault Duty Cycle VFB = 2.7V, Measure GATE(H) Pulse Width VFB = 0V 30 50 70 % 10 30 50 s VFB = 2.7V VSS = VFB = 0V 1.0 5.0 1.6 8.0 2.3 12.0 s s
s Voltage Identification DAC Accuracy (all codes except 11111) Measure VFB = COMP, (COFF = Gnd) VID4 VID3 VID2 VID1 VID0 25C TJ 125C, VCC = 12V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 4
-1.0 3.489 3.390 3.291 3.192 3.093 2.994 2.895 2.796 2.697 2.598 2.499 2.400 2.301 2.202 2.103 2.054 2.004 1.955 1.905 3.525 3.425 3.325 3.225 3.125 3.025 2.925 2.825 2.725 2.625 2.525 2.425 2.325 2.225 2.125 2.075 2.025 1.975 1.925
1.0 3.560 3.459 3.358 3.257 3.156 3.055 2.954 2.853 2.752 2.651 2.550 2.449 2.348 2.247 2.146 2.095 2.045 1.994 1.944
% V V V V V V V V V V V V V V V V V V V
CS5166
Electrical Characteristics: 0C < TA < 70C; 0C < TJ < 125C; 8V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1F; Unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Accuracy (all codes except 11111) Measure VFB = COMP, (COFF = Gnd) VID4 VID3 VID2 VID1 VID0 0 0 1 00 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 1 VID4, VID3, VID2, VID1, VID0 VID4, VID3, VID2, VID1, VID0
-1.0 1.856 1.806 1.757 1.707 1.658 1.608 1.559 1.509 1.460 1.410 1.361 1.311 1.219 1.0 25 4.85 1.875 1.825 1.775 1.725 1.675 1.625 1.575 1.525 1.475 1.425 1.375 1.325 1.247 1.25 50 5.00
1.0 1.893 1.843 1.792 1.742 1.691 1.641 1.590 1.540 1.489 1.439 1.388 1.338 1.269 2.4 100 5.15
% V V V V V V V V V V V V V V k V
Input Threshold Input Pull-up Resistance Input Pull-up Voltage s Power-Good Output Low to High Delay High to Low Delay Output Low Voltage Sink Current Limit
VFB = (0.8 x VDAC ) to VDAC VFB = VDAC to (0.8 x VDAC ) VFB = 2.4V, IPWRGD = 500A VFB = 2.4V, PWRGD = 1V
30 30 0.5
65 75 0.2 4.0
110 120 0.3 15.0
s s V mA
THRESHOLD ACCURACY
LOWER THRESHOLD MIN TYP MAX
UPPER THRESHOLD MIN TYP MAX UNITS
% of Nominal VID Code s DAC CODE VID4 VID3 VID2 VID1 VID0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0
-12
-8.5
-5
5
8.5
12
%
3.102 3.014 2.926 2.838 2.750 2.662 2.574 2.486 2.398 2.310 2.222
3.225 3.133 3.042 2.950 2.859 2.767 2.676 2.584 2.493 2.401 2.310 5
3.348 3.253 3.158 3.063 2.968 2.873 2.778 2.683 2.588 2.493 2.398
3.701 3.596 3.491 3.386 3.281 3.176 3.071 2.966 2.861 2.756 2.651
3.824 3.716 3.607 3.499 3.390 3.282 3.173 3.065 2.956 2.848 2.739
3.948 3.836 3.724 3.612 3.500 3.388 3.276 3.164 3.052 2.940 2.828
V V V V V V V V V V V
CS5166
Electrical Characteristics: 0C < TA < 70C; 0C < TJ < 125C; 8V < VCC < 14V; 2.0V DAC Code (VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1F; Unless otherwise stated.
THRESHOLD ACCURACY LOWER THRESHOLD MIN TYP MAX UPPER THRESHOLD MIN TYP MAX UNITS
% of Nominal VID Code s DAC CODE VID4 VID3 VID2 VID1 VID0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
-12
-8.5
-5
5
8.5
12
%
2.134 2.046 1.958 1.870 1.826 1.782 1.738 1.694 1.650 1.606 1.562 1.518 1.474 1.430 1.386 1.342 1.298 1.254 1.210 1.166 1.094
2.218 2.127 2.035 1.944 1.898 1.8520 1.807 1.761 1.715 1.669 1.624 1.578 1.532 1.486 1.441 1.395 1.349 1.303 1.258 1.212 1.138
2.303 2.208 2.113 2.018 1.971 1.923 1.876 1.828 1.781 1.733 1.686 1.638 1.591 1.543 1.496 1.448 1.401 1.353 1.306 1.258 1.181
2.546 2.441 2.336 2.231 2.178 2.126 2.073 2.021 1.968 1.916 1.863 1.811 1.758 1.706 1.653 1.601 1.548 1.496 1.443 1.391 1.306
2.631 2.522 2.414 2.305 2.251 2.197 2.142 2.088 2.034 1.980 1.925 1.871 1.817 1.763 1.708 1.654 1.600 1.546 1.491 1.437 1.349
2.716 2.604 2.492 2.380 2.324 2.268 2.212 2.156 2.100 2.044 1.988 1.932 1.876 1.820 1.764 1.708 1.652 1.596 1.540 1.484 1.393
V V V V V V V V V V V V V V V V V V V V V
Note 1: Guaranteed by design, not 100% tested in production Block Diagram
-
VCC Monitor
+
VCC
3.95V 3.87V
5V
60A 0.7V
+
SS Low Comparator
VGATE(H)
R S Q Q
FAULT FAULT
PGnd
SS
2A
2.5V ERROR AMPLIFIER
+
+ -
SS High Comparator
FAULT Latch
VCC
VGATE(L) PGnd
COMP VID0
VID1
VID2 VID3 VID4 -8.5%
5 BIT DAC
PWM COMPARATOR
+
-
PWM Comp Blanking
Maximum On-Time Timeout
R S Q Q
GATE(H) = ON GATE(H) = OFF
VCC
+8.5%
-
76mV
30A
-
Normal Off-Time Extended Off-Time Timeout
PWM Latch Off-Time Timeout
COFF One Shot
R S Q
+
+
COFF
PWRGD
+
65S Delay
COMPARATOR
+
ISENSE
VFB ISENSE
LGnd
1V
Time Out Timer
Edge Triggered
VFB LOW COMPARATOR
6
CS5166
Application Information Theory Of Operation V2TM Control Method The V2TM method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current.
PWM Comparator
+ GATE(H) C - GATE(L)
of the CS5166 single pole feedback loop and demonstrates the overall stability of the CS5166-based regulator.
.1F 10K Open Loop 49.63 BW 62.3 KHz Phase margin 81.9
Figure 2: Feedback loop Bode Plot.
Ramp Signal VFB
Error Amplifier COMP Error Signal
E
- +
Reference Voltage
Figure 1: V2
2TM
TM
Control Diagram.
The V control method is illustrated in Figure 1. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2TM control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2TM control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this `slow' feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. The Bode plot in Figure 2 shows the gain and phase margin
Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2TM method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. Constant Off-Time To maximize transient response, the CS5166 uses a Constant Off-Time method to control the rate of output pulses. During normal operation, the Off-Time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2TM Control Loop varies switch On-Time. The PWM comparator monitors the output voltage ramp, and terminates the switch On-Time. Constant Off-Time provides a number of advantages. Switch duty Cycle can be adjusted from 0 to 100% on a pulse-by pulse basis when responding to transient conditions. Both 0% and 100% Duty Cycle operation can be maintained for extended periods of time in response to Load or Line transients. PWM Slope Compensation to avoid sub-harmonic oscillations at high duty cycles is avoided. Switch On-Time is limited by an internal 30s (typical) timer, minimizing stress to the Power Components Programmable Output The CS5166 is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. 7
CS5166
Application Information: continued The first range is 2.125V to 3.525V in 100mV steps, the second is 1.325V to 2.075V in 50mV steps, depending on the digital input code. If all five bits are left open, the CS5166 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB pin, as in traditional controllers. The CS5166 is specifically designed to meet or exceed Intel's Pentium(R) II specifications. Start-up Until the voltage on the VCC Supply pin exceeds the 3.95V monitor threshold, the Soft Start and Gate pins are held low. The Fault latch is Reset (no Fault condition). The output of the Error Amp (COMP) is pulled up to 1V by the Comp Clamp. When the VCC pin exceeds the monitor threshold, the GATE(H) output is activated, and the Soft Start Capacitor begins charging. The GATE(H) output will remain on, enabling the NFET switch, until terminated by either the PWM Comparator, or the Maximum On-Time Timer. If the Maximum On-Time is exceeded before the regulator output voltage achieves the 1V level, the pulse is terminated. The GATE(H) pin drives low, and the GATE(L) pin drives high for the duration of the Extended Off-Time. This time is set by the Time-out Timer and is approximately equal to the Maximum On-Time, resulting in a 50% Duty Cycle. The GATE(L) Pin will then drive low, the GATE(H) pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1V level present at the Comp pin, regulation has been achieved and normal Off-Time will ensue. The PWM comparator terminates the switch On-Time, with Off-Time set by the COFF Capacitor. The V2TM control loop will adjust switch Duty Cycle as required to ensure the regulator output voltage tracks the output of the Error Amp. The Soft Start and Comp capacitors will charge to their final levels, providing a controlled turn-on of the regulator output. Regulator turn-on time is determined by the Comp capacitor charging to its final value. Its voltage is limited by the Soft Start Comp clamp and the voltage on the Soft Start pin.
Trace 1 - Regulator Output Voltage (1V/div.) Trace 3 - COMP Pin (error amplifier output) (1V/div.) Trace 4 - Soft Start Pin (2V/div.)
Figure 4: Demonstration board startup waveforms.
Trace 1 - Regulator Output Voltage (5V/div.) Trace 2 - Inductor Switching Node (5V/div.)
Figure 5: Demonstration board enable startup waveforms.
Normal Operation During Normal operation, Switch Off-Time is constant and set by the COFF capacitor. Switch On-Time is adjusted by the V2TM Control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current and the ESR of the output capacitors (see Figures 6 and 7).
Trace 1 - Regulator Output Voltage (1V/div.) Trace 2 - Inductor Switching Node (2V/div.) Trace 3 - 12V input (VCC) (5V/div.) Trace 4 - 5V Input (1V/div.)
Figure 3: Demonstration board startup in response to increasing 12V and 5V input voltages. Extended off time is followed by normal off time operation when output voltage achieves regulation to the error amplifier output.
8
CS5166
Application Information: continued back pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +25mV offset. When the full load current is delivered, a 50mV drop is developed across this resistor. This results in output voltage being offset 25mV low. The result of Adaptive Voltage Positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre-positioned +25mV. Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre-positioned -25mV (see Figures 8, 9, and 10). For best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used. If the Maximum On-Time is exceeded while responding to a sudden increase in Load current, a normal off-time occurs to prevent saturation of the output inductor.
Trace 1 GATE (H) (10V/div) Trace 2 Inductor Switching Node (5V/div) Trace 3 Output Inductor Ripple Current (2A/div) Trace 4 VOUT ripple (20mV/div)
Figure 6: Normal Operation showing Output Inductor Ripple Current and Output Voltage Ripple, 0.5A Load, VOUT = +2.825V (DAC = 10111).
Trace 1 - GATE(H) (10/div) Trace 2 - Inductor Switching Node (5V/div) Trace 3 - Output Inductor Ripple Current (2A/div) Trace 4 - VOUT ripple (20mV/div)
Figure 7: Normal Operation showing Output Inductor Ripple Current and Output Voltage Ripple, ILOAD = 14A, VOUT = +2.825V (DAC = 10111).
Trace 3 -Load Current (5A/10mV/div) Trace 4 - VOUT (100mV/div)
Figure 8: Output Voltage Transient Response to a 14A load pulse, VOUT= 2.825V (DAC = 10111).
Transient Response The CS5166 V2TM Control Loop's 150ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called "Adaptive Voltage Positioning". This technique pre-positions the output capacitors voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1% allows the error amplifiers reference voltage to be targeted +25mV high without compromising DC accuracy. A "Droop Resistor", implemented through a PC board trace, connects the Error Amps feed9
Trace 1 - GATE(H) (10V/div) Trace 2 - Inductor Switching Node (5V/div) Trace 3 -Load Current (5A/div) Trace 4 - VOUT (100mV/div)
Figure 9: Output Voltage Transient Response to a 14A load step, VOUT = 2.825V (DAC = 10111).
CS5166
Application Information: continued traces, as the over current condition persists. Upon removal of the overload, the fault latch is cleared, allowing normal operation to resume. The current limit trip point can be adjusted through an external resistor, providing the user with the current limit set-point flexibility.
Trace 1 - GATE(H) (10V/div) Trace 2 - Inductor Switching Node (5V/div) Trace 3 -Load Current (5A/div) Trace 4 - VOUT(100mV/div)
Figure 10: Output Voltage Transient Response to a 14A load turn-off, VOUT = +2.825V (DAC = 10111).
Power Supply Sequencing The CS5166 offers inherent protection from undefined start-up conditions, regardless of the 12V and 5V supply power-up sequencing. The turn-on slew rates of the 12V and 5V power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator.
Trace 4 - 5V Supply Voltage (2V/div.) Trace 3 - Soft Start Timing Capacitor (1V/div.) Trace 2 - Inductor Switching Node (2V/div.)
Figure 11: Demonstration board hiccup mode short circuit protection. Gate pulses are delivered while the Soft Start capacitor charges, and cease during discharge.
Protection and Monitoring Features Over-Current Protection A loss-less hiccup mode current limit protection feature is provided, requiring only the Soft Start capacitor to implement. The CS5166 provides overcurrent protection by sensing the current through a "Droop" resistor, using an internal current sense comparator. The comparator compares this voltage drop to an internal reference voltage of 76mV (typical). If the voltage drop across the "Droop" resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. This causes the regulator to stop switching. During this over current condition, the CS5166 stays off for the time it takes the Soft Start capacitor to slowly discharge by a 2A current source until it reaches its lower 0.7V threshold. At that time the regulator attempts to restart normally by delivering short gate pulses to both FETs. The CS5166 will operate initially in its extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60A charge current. The gates will switch on while the Soft Start capacitor is charged to its upper 2.7V threshold. During an overload condition the Soft Start charge /discharge current ratio sets the duty cycle for the pulses (2A/60A = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%) when VFB is less than 1V. The Soft Start hiccup pulses last for a 3ms period at the end of which the duty cycle repeats if a fault is detected, otherwise normal operation resumes. This protection scheme minimizes thermal stress to the regulator components, input power supply, and PC board 10
Trace 4 = 5V from PC Power Supply (2V/div.) Trace 2 = Inductor Switching Node (2V/div.)
Figure 12: Demonstration board Start up with regulator output shorted to ground.
Overvoltage Protection Overvoltage protection (OVP) is provided as result of the normal operation of the V2TM control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100ns, causing the top MOSFET to shut off, disconnecting the regulator from its input voltage. The bottom MOSFET is then activated, resulting in a "crowbar" action to clamp the output voltage and prevent damage to the load (see Figures 13 and 14). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function. If a dedicated OVP output is required, it can be implemented using the circuit in Figure 15. In this figure the OVP signal will go high (overvoltage condition), if the output voltage (VCORE) exceeds 20% of the voltage set by the particular DAC code
CS5166
Application Information: continued and provided that PWRGD is low. It is also required that the overvoltage condition be present for at least the PWRGD delay time for the OVP signal to be activated. The resistor values shown in Figure 15 are for VDAC = +2.8V (DAC = 10111). The VOVP (overvoltage trip-point) can be set using the following equation:
VCORE
15K
R1
Q3 2N3906
+5V 56K 5K
R2
VOVP = VBEQ3 1 +
(
R2 R1
)
CS5166 PWRGD
OVP 20K +5V
Q2 2N3904
10K 10K
10K
Q1 2N3906
Figure 15: Circuit to implement a dedicated OVP output using the CS5166.
Power-Good Circuit The Power-Good pin (pin 13) is an open-collector signal consistent with TTL DC specifications. It is externally pulled -up, and is pulled low (below 0.3V) when the regulator output voltage typically exceeds 8.5% of the nominal output voltage. Maximum output voltage deviation before Power-Good is pulled low is 12%.
Trace 4 = 5V from PC Power Supply (5V/div.) Trace1 = Regulator Output Voltage (1V/div.) Trace 2 = Inductor Switching Node (5V/div.)
Figure 13: OVP response to an input-to-output short circuit by immediately providing 0% duty cycle, crow-barring the input voltage to ground.
2.825V
Trace 2 - PWRGD (2V/div) Trace 4 - VOUT (1V/div)
Figure 16: PWRGD signal becomes logic high as VOUT enters -8.5% of lower PWRGD threshold, VOUT = +2.825V (DAC = 10111).
Trace 4 = 5V from PC Power Supply (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.)
Figure 14: OVP response to an input-to-output short circuit by pulling the input voltage to ground.
Trace 1 PWRGD (2V/div) Trace 4 VFB (1V/div)
Figure 17: Power-Good response to an out of regulation condition.
11
CS5166
Application Information: continued Figure 17 shows the relationship between the regulated output voltage VFB and the Power-Good signal. To prevent Power-Good from interrupting the CPU unnecessarily, the CS5166 has a built-in delay to prevent noise at the VFB pin from toggling Power-Good. The internal time delay is designed to take about 75s for Power-Good to go low and 65s for it to recover. This allows the Power-Good signal to be completely insensitive to out of regulation conditions that are present for a duration less than the built in delay (see Figure 18). It is therefore required that the output voltage attains an out of regulation or in regulation level for at least the builtin delay time duration before the Power-Good signal can change state. Selecting External Components The CS5166 buck regulator can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. NFET Power Transistors Both logic level and standard FETs can be used. The reference designs derive gate drive from the 12V supply which is generally available in most computer systems and utilize logic level FETs. A charge pump may be easily implemented to support 5V only systems. Multiple FET's may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5V of ground when in the low state and to within 2V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC = 12V and 5V is used as the source for the regulator output current, the following gate drive is provided:
VGS (TOP) = 12V - 5V = 7V, VGS(BOTTOM) = 12V, (see Figure 20).
Trace 1 PWRGD (2V/div) Trace 4 VFB (1V/div)
Figure 18: Power-Good is insensitive to out of regulation conditions that are present for a duration less than the built in delay.
External Output Enable Circuit On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 19). This circuit operates by pulling the Soft Start pin high, and the ISENSE pin low, emulating a current limit condition.
5V
MMUN2111T1 (SOT-23)
Trace 3 = GATE(H) (10V/div.) Trace 1= GATE(H) - 5VIN Trace 4 = GATE(L) (10V/div.) Trace 2 = Inductor Switching Node (5V/div.)
5
Figure 20: Gate drive waveforms depicting rail to rail swing.
SS
CS5166
8I SENSE
IN4148
Shutdown Input
Figure 19: Implementing shutdown with the CS5166.
12
CS5166
Application Information: continued
where period =
1 . switching frequency
Trace 1 - GATE(H) (5V/div) Trace 2 - GATE(L) (5V/div)
Figure 21: Normal Operation showing the guaranteed Non-Overlap time between the High and Low - Side MOSFET Gate Drives, ILOAD = 14A.
Schottky Diode for Synchronous FET For synchronous operation, A Schottky diode may be placed in parallel with the synchronous FET to conduct the inductor current upon turn off of the switching FET to improve efficiency. The CS5166 reference circuit does not use this device due to its excellent design. Instead, the body diode of the synchronous FET is utilized to reduce cost and conducts the inductor current. For a design operating at 200kHz or so, the low non-overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense. The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power = Vbd x ILOAD x conduction time x switching frequency Where Vbd = the forward drop of the MOSFET body diode. For the CS5166 demonstration board: Power = 1.6V x 14.2A x 100ns x 200kHz = 0.45W This is only 1.1% of the 40W being delivered to the load. "Droop" Resistor for Adaptive Voltage Positioning Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To implement adaptive voltage positioning a "Droop Resistor" must be connected between the output inductor and output capacitors and load. This resistor carries the full load current and should be chosen so that both DC and AC tolerance limits are met. An embedded PC trace resistor has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation causes the thickness of the PCB layer to vary. 2) the mismatch of L/W, and 3) temperature variation. 1) Sheet Resistivity for one ounce copper, the thickness variation is typically 1.15 mil to 1.35 mil. Therefore the error due to sheet resistivity is: 1.35 - 1.15 1.25 = 16%
The CS5166 provides adaptive control of the external NFET conduction times by guaranteeing a typical 65ns non-overlap (as seen in Figure 21) between the upper and lower MOSFET gate drive pulses. This feature eliminates the potentially catastrophic effect of "shoot-through current", a condition during which both FETs conduct causing them to overheat, self-destruct, and possibly inflict irreversible damage to the processor. The most important aspect of FET performance is RDSON, which effects regulator efficiency and FET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows: Switching MOSFET: Power = ILOAD2 x RDSON x duty cycle Synchronous MOSFET: Power = ILOAD2 x RDSON x (1 - duty cycle) Duty Cycle =
VOUT + (ILOAD x RDSON OF SYNCH FET) VIN + (ILOAD x RDSON OF SYNCH FET) - (ILOAD x RDSON OF SWITCH FET)
Off Time Capacitor (COFF) The COFF timing capacitor sets the regulator off time: TOFF = COFF x 4848.5 The preceding equation for Duty Cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor: COFF =
Period x (1-Duty Cycle) 4848.5
2) Mismatch due to L/W The variation in L/W is governed by variations due to the PCB manufacturing process that affect the geometry and the power dissipation capability of the droop resistor. The error due to L/W mismatch is typically 1%
13
CS5166
Application Information: continued 3) Thermal Considerations Due to I2 x R power losses the surface temperature of the droop resistor will increase causing the resistance to increase. Also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula: R = R20 [1+ 20(-20)] where: R20 = resistance at 20C = 0.00393 C the DC accuracy spec, the voltage drop developed across the resistor must be calculated as follows: VDROOP(TYP) = [VDAC(MIN)-VDC PENTIUM(R)II(MIN)] 1+RDROOP(TOLERANCE) 2.796V-2.74V 1.3 = 43mV
=
T= operating temperature R = desired droop resistor value For temperature T = 50C, the % R change = 12% Droop Resistor Tolerance Tolerance due to sheet resistivity variation 16% Tolerance due to L/W error 1% Tolerance due to temperature variation 12% Total tolerance for droop resistor 29% In order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. This voltage drop has to be such that the output voltage full load is above the minimum DC tolerance spec. VDROOP(TYP) = [VDAC(MIN)-VDC(MIN)] 1+RDROOP(TOLERANCE)
With the CS5166 DAC accuracy being 1%, the internal error amplifier's reference voltage is trimmed so that the output voltage will be 25mV high at no load. With no load, there is no DC drop across the resistor, producing an output voltage tracking the error amplifier output voltage, including the offset. When the full load current is delivered, a drop of -43mV is developed across the resistor. Therefore, the regulator output is pre-positioned at 25mV above the nominal output voltage before a load turn-on. The total voltage drop due to a load step is V-25mV and the deviation from the nominal output voltage is 25mV smaller than it would be if there was no droop resistor. Similarly at full load the regulator output is pre-positioned at 18mV below the nominal voltage before a load turn-off. the total voltage increase due to a load turn-off is V-18mV and the deviation from the nominal output voltage is 18mV smaller than it would be if there was no droop resistor. This is because the output capacitors are pre-charged to value that is either 25mV above the nominal output voltage before a load turn-on or, 18mV below the nominal output voltage before a load turn-off (see Figure 8). Obviously, the larger the voltage drop across the droop resistor (the larger the resistance), the worse the DC and load regulation, but the better the AC transient response. Current Limit Setpoint Calculations The following is the design equation used to set the current limit trip point by determining the value of the embedded PCB trace used as a current sensing element. The current limit setpoint has to be higher than the normal full load current. Attention has to be paid to the current
Example: for a 300MHz Pentium(R)II, the DC accuracy spec is 2.74 < VCC(CORE) < 2.9V, and the AC accuracy spec is 2.67V < VCC(CORE) <2.93V. The CS5166 DAC output voltage is +2.796V < VDAC < +2.853V. In order not to exceed
VIN
CS5166
IFB
RFB Current Limit Comparator
VFB ISENSE
Q1 L RDROOP
VOUT
+ VTH
ISENSE
Q2
COUT
RISENSE
ISENSE
Figure 22: Circuit used to determine the voltage across the droop resistor that will trip the internal current sense comparator.
14
CS5166
Application Information: continued rating of the external power components as these are the first to fail during an overload condition. The MOSFET continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the current limit trip point. For example the IRL 3103S (D2 PAK) MOSFET has a continuous drain current rating of 45A at VGS = 10V and TC = 100C. Temperature curves on MOSFET manufacturers' data sheets allow the designer to determine the MOSFET drain current at a particular VGS and TJ (junction temperature). This, in turn, will assist the designer to set a proper current limit, without causing device breakdown during an overload condition. For a 300MHz Pentium (R) II CPU the full load is 14.2A. The internal current sense comparator current limit voltage limits are: 55mV < VTH < 130mV. Also, there is a 29% total variation in RSENSE as discussed in the previous section. We select the value of the current sensing element (embedded PCB trace) for the minimum current limit setpoint: RSENSE(MAX) = VTH(MIN) 55mV RSENSE x 1.29 = ICL(MIN) 14.2A ISENSE and VFB pins. These are needed for proper current limit operation and the resistor value is layout dependent. This series resistor affects the calculation of the current limit setpoint, and has to be taken into account when determining an effective current limit. The calculations below show how the current limit setpoint is determined when this 510 is taken into consideration. VTRIP = VTH + (ISENSE x RISENSE) - (RFB x IFB) Where VTRIP = voltage across the droop resistor that trips the ISENSE comparator VTH = internal ISENSE comparator threshold ISENSE = ISENSE bias current RISENSE = ISENSE pin 510 filter resistor RFB = VFB pin 3.3K filter resistor IFB = VFB bias current Minimum current sense resistor (droop resistor) voltage drop required for current limit when RISENSE is used VTRIP(MIN) = 55mV + (13A x 510) - (3.3K x 1A) = 55mV + 6.6mV - 3.3mV = 58.3mV Nominal current sense resistor (droop resistor) voltage drop required for current limit when RISENSE is used VTRIP(NOM) = 76mV + (30A x 510) - (3.3K x 0.1A) = 76mV + 15.3mV - 0.33mV = 90.97mV Maximum current sense resistor (droop resistor) voltage drop required for current limit when RISENSE is used VTRIP(MAX) = 110mV + (50A x 510) = 110mV + 25.5mV = 135.5mV The value of RSENSE (current sense PCB trace) is then calculated: 58.3mV RSENSE(MAX) = = 4.1m 14.2A 110mV 110mV = = 51.6A RSENSE x 0.71 3m x 0.71 RSENSE(MAX) = 1.29 4.1mm 1.29
RSENSE x 1.29 = 3.87m RSENSE = 3m We calculate the range of load currents that will cause the internal current sense comparator to detect an overload condition. From the overcurrent detection data section (pg 3), Nominal Current Limit Setpoint VTH(TYP) = 76mV. ICL(NOM) = VTH(TYP) RSENSE(NOM)
Maximum Current Limit Setpoint Therefore , ICL(NOM) = VTH(MAX) = 110mV. Therefore, ICL(MAX) = 110mV RSENSE(MIN) = 76mV 3m = 25.3A
RSENSE(NOM) =
= 3.18m
Therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3m embedded PCB trace is: 14.2A < ICL < 51.6A, with 25.3A being the nominal overload condition. There may be applications whose layout will require the use of two extra filter components, a 510 resistor in series with the ISENSE pin, and a 0.1F capacitor between the 15
The range of load currents that will cause the internal current sense comparator to detect an overload condition is as follows: Nominal Current Limit Setpoint ICL(NOM) = VTRIP(NOM) / RSENSE(NOM) Therefore, ICL(NOM) = 90.97mV / 3.18m = 28.6A
CS5166
Application Information: continued Maximum Current Limit Setpoint ICL(MAX) = VTRIP(MAX) / RSENSE(MAX) Therefore, ICL(MAX) = 135mV / 3.18m x 0.71 = 60A Therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3m embedded PCB trace is: 14.2A < ICL 60A, with 28.6A being the nominal overload condition. Design Rules for Using a Droop Resistor The basic equation for laying an embedded resistor is: RAR = x L A or R=x L (W x t) L= length (mils) W = width (mils) t = thickness (mils) For most PCBs the copper thickness, t, is 35m (1.37 mils) for one ounce copper. = 717.86-mil For a Pentium(R)II load of 14.2A the resistance needed to create a 43mV drop at full load is: RDROOP = 43mV IOUT = 43mV 14.2A = 3.0m
The resistivity of the copper will drift with the temperature according to the following guidelines: R = 12% @ TA = +50C R = 34% @TA = +100C Droop Resistor Width Calculations The droop resistor must have the ability to handle the load current and therefore requires a minimum width which is calculated as follows (assume one ounce copper thickness):
5V
where: A= W x t = cross-sectional area = the copper resistivity ( - mil)
12V
1200F/10V x 3
1F COFF 330pF 0.1F 0.1F
SS
COMP
VCC
GATE(H)
IRL3103S
1.2H
3.0m 510
1200F 10V x 5
ISENSE
2.8V/30A Power Supply
CS5166
0.1F
GATE(L)
VID0 VID1 VID2 VID3
VID4
PWRGD PGnd LGnd
IRL3103S
PWRGD
VFB
3.3K
VID4
1000pF
VID3 VID2
VID1
VID0 5V 12V
1200F/10V x 3
1F COFF 330pF 0.1F
SS
COMP
VCC
GATE(H)
IRL3103S
1.2H
3.0m 510
ISENSE
CS5166
0.1F
GATE(L)
VID0 VID1 VID2 VID3
VID4 VFB
IRL3103S
PGnd LGnd
3.3K
1000pF
Figure 23: Current sharing of a 2.8V/30A power supply using two CS5166 synchronous buck regulators.
16
CS5166
Application Information: continued ILOAD 0.05 The output current of each regulator can be calculated from: IN = (VOUT(N) - VOUT) / RDROOP(N) where: W = minimum width (in mils) required for proper power dissipation, and ILOAD Load Current Amps. The Pentium(R)II maximum load current is 14.2A. Therefore: 14.2A W= = 284 mils = 0.7213cm 0.05 Droop Resistor Length Calculation L= RDROOP x W x t 0.0030 x 284 x 1.37 = = 1626 mil = 4.13cm 717.86 where: VOUT(N) and RDROOP(N) are the output voltage and droop resistance of a particular regulator and VOUT is the system output voltage. Output current is the sum of each regulator's current: IOUT = I1 + I2 + ... + IN Current sharing improves with increasing load current. The increasing voltage drop across the droop resistor due to increasing load current eventually swamps out the differences in regulator output voltages. If a large enough voltage can be developed across the droop resistors, current sharing accuracy will be determined solely by their matching. To realize the benefits of current sharing, it is not necessary to obtain perfect matching. Keeping output currents within +/- 10% is usually acceptable. For microprocessor applications, the value of the droop resistor must be selected to optimize adaptive voltage positioning, current sharing, current limit and efficiency. Current sharing is realized by simply connecting the COMP pins of the respective buck regulators, as shown in Figure 23. Figure 24 shows operation with no load. In this case, there is insufficient output voltage ripple across the droop resistors to produce complete synchronization. Duty Cycle is close to the theoretical 56% (VOUT/VIN) resulting in a switching frequency of approximately 275kHz. Figure 25 shows operation with a 30 Amp load. Synchronization between the two regulators is now obtained due to increased ripple voltage. Increased losses cause the V2TM control loop to increase on-time to compensate. This results in a larger duty cycle and a corresponding decrease in switching frequency to 233kHz.
W=
Implementing current sharing using the "Droop Resistor" In addition to improving load transient performance, the CS5166 V2TM control method allows the droop resistor to provide the additional capability to easily implement current sharing. Figure 23 shows a simplified schematic of two current sharing synchronous buck regulators. Each buck regulator's droop resistor is terminated at the load. The PWM control signal from each Error Amp is connected together, causing the inner PWM loop to regulate to a common voltage. Since the voltage at each resistor terminal is the same, this configuration results in equal voltage being applied across each matched droop resistor. The result is equal current flowing through each buck regulator. An additional benefit is that synchronization to a common switching frequency tends to be achieved because each regulator shares a common PWM ramp signal. In practice, each buck regulator will regulate to a slightly different output voltage due to mismatching of the PWM comparators, slope of the PWM ramp (output voltage ripple), and propagation delays. At light loads, the result can be very poor current sharing. With zero output current, some regulators may be sourcing current while others may be sinking current. This results in additional power dissipation and lower efficiency than would be obtained by a single regulator. This is usually not an issue since efficiency is most important when a supply is fully loaded. This effect is similar to the difference in efficiency between synchronous and non-synchronous buck regulators. Synchronous Buck regulators have lower efficiency at light loads because inductor current is always continuous, flowing from the load to ground during switch off-time through the synchronous rectifier. Under full load conditions, the synchronous design is more efficient due to the lower voltage drop across the synchronous rectifier. Likewise, the efficiency of droop sharing regulators will be lower at light loads due to the continuous current flow in the droop resistors. Efficiency at heavy loads tends to be higher due to reduced I2R losses. 17
Trace 1 Output voltage ripple Trace 2 Buck regulator #1 inductor switching node Trace 3 Buck regulator #2 inductor switching node
Figure 24: No load waveforms.
CS5166
Application Information: continued Inductor Ripple Current Ripple current =
(Switching Frequency
[(VIN - VOUT) x VOUT] x L x VIN)
Example: VIN = +5V, VOUT = +2.8V, ILOAD = 14.2A, L = 1.2H, Freq = 200KHz Ripple current = [(5V-2.8V) x 2.8V] [200KHz x 1.2H x 5V] = 5.1A
Trace 1 Output voltage ripple Trace 2 Buck regulator #1 inductor switching node Trace 3 Buck regulator #2 inductor switching node
Output Ripple Voltage VRIPPLE = Inductor Ripple Current x Output Capacitor ESR Example: VIN = +5V, VOUT = +2.8V, ILOAD = 14.2A, L = 1.2H, Switching Frequency = 200KHz Output Ripple Voltage = 5.1A x Output Capacitor ESR (from manufacturer's specs) ESR of Output Capacitors to limit Output Voltage Spikes ESR = VOUT IOUT
Figure 25: 30A load waveforms.
Trace 1 Output voltage ripple Trace 2 Buck regulator #1 inductor switching node Trace 3 Buck regulator #2 inductor switching node
This applies for current spikes that are faster than regulator response time. Printed Circuit Board resistance will add to the ESR of the output capacitors. In order to limit spikes to 100mV for a 14.2A Load Step, ESR = 0.1/14.2 = 0.007 Inductor Peak Current Peak Current = Maximum Load Current +
Figure 26: 15A load transient waveforms.
Figure 26 shows supply response to a 15A load step with a 30A/s slew rate. The V2TM control loop immediately forces the duty cycle to 100%, ramping the current in both inductors up. A voltage spike of 136mV due to output capacitor impedance occurs. The inductive component of the spike due to ESL recovers within several microseconds. The resistive component due to ESR decreases as inductor current replaces capacitor current. The benefit of adaptive voltage positioning in reducing the voltage spike can readily be seen. The differences in DC voltage and duty cycle can also be observed. This particular transient occurred near the beginning of regulator offtime, resulting in a longer recovery time and increased voltage spike. Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response.
(
Ripple Current 2
)
Example: VIN = +5V, VOUT = +2.8V, ILOAD = 14.2A, L = 1.2H, Freq = 200KHz
Peak Current = 14.2A + (5.1/2) = 16.75A A key consideration is that the inductor must be able to deliver the Peak Current at the switching frequency without saturating. Response Time to Load Increase (limited by Inductor value unless Maximum On-Time is exceeded) Response Time = L x IOUT (VIN-VOUT)
Example: VIN = +5V, VOUT = +2.8V, L = 1.2H, 14.2A change in Load Current Response Time = 1.2H x 14.2A (5V-2.8V) = 7.7s
18
CS5166
Application Information: continued Response Time to Load Decrease (limited by Inductor value) L x Change in IOUT VOUT
33 2H
Response Time =
2H +
1200F x 3/16V
Example: VOUT = +2.8V, 14.2A change in Load Current, L = 1.2H Response Time = 1.2H x 14.2A 2.8V = 6.1s
1000pF
Figure 27: Filter components.
Figure 28: Input Filter.
Input and Output Capacitors These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. Thermal Management Thermal Considerations for Power MOSFETs and Diodes In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: Thermal Impedance = TJ(MAX) - TA Power
Layout Guidelines When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS5166. 1) Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2) Keep high currents out of sensitive ground connections. Avoid connecting the IC Gnd (LGnd) between the source of the lower FET and the input capacitor Gnd. 3) Avoid ground loops as they pick up noise. Use star or single point grounding. 4) For high power buck regulators on double-sided PCBs a single large ground plane (usually the bottom) is recommended. 5) Even though double-sided PCBs are usually sufficient for a good layout, four-layer PCBs are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the +5V and Gnd planes, the top layer for the power connections and component vias, and the bottom layer for the noise sensitive traces. 6) Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7) The FET gate traces to the IC must be as short, straight, and wide as possible. Ideally, the IC has to be placed right next to the FETs. 8) Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9) Place the switching FET as close to the +5V input capacitors as possible. 10) Place the output capacitors as close to the load as possible.
A heatsink may be added to TO-220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. EMI Management As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions.
19
CS5166
Application Information: continued 11) Place the VFB filter resistor in series with the VFB pin (pin 16) right at the pin. 12) Place the VFB filter capacitor right at the VFB pin (pin 16). 13) The "Droop" Resistor (embedded PCB trace) has to be wide enough to carry the full load current. 14) Place the VCC bypass capacitor as close as possible to the VCC pin and connect it to the PGnd pin of the IC. Connect the PGnd pin directly to the Gnd plane. 15) Create a subground (local Gnd) plane preferably on the PCB top layer and under the IC controller. Connect all logic capacitor returns and the LGnd pin of the IC to this plane. Connect the subground plane to the main Gnd plane using a minimum of four (4) vias.
Typical Performance Characteristics
200 180 160 140 120 100 80 60 40 20 0 0 2000 4000
VCC=12V TA=25C
6000 8000 10000 12000 14000 16000 Load Capacitance (pF)
200 180 160 140 120 100 80 60 40 20 0 0 2000 4000
Risetime (ns)
Risetime (ns)
VCC=12V TA=25C
6000 8000 10000 12000 14000 16000 Load Capacitance (pF)
Figure 29: GATE(L) Risetime vs. Load Capacitance.
Figure 32: GATE(H) Risetime vs. Load Capacitance.
DAC Output Voltage Deviation (%)
200 180 160 140 120 100 80 60 40 20 0 0 2000 4000
0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 0 20 40 60 80 100 120 Junction Temperature (C)
Falltime (ns)
VCC=12V TA=25C
6000 8000 10000 12000 14000 16000 Load Capacitance (pF)
Figure 30: GATE(H) & GATE(L) Falltime vs. Load Capacitance.
Figure 33: DAC Output Voltage vs Temperature, DAC Code = 10111, VCC = 12V.
0.04
0.05
Output Error (%)
0 -0.02 -0.04 -0.06 -0.08 -0.1 1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075
Output Error (%)
DAC Output Voltage Setting (V)
0.02
0 -0.05 -0.1 -0.15 -0.2 -0.25 2.125 2.225 2.325 2.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.325 3.425 3.525
DAC Output Voltage Setting (V)
Figure 31: Percent Output Error vs DAC Voltage Setting, VCC = 12V, TA = 25C, VID4 = 0.
Figure 34: Percent Output Error vs. DAC Output Voltage Setting VCC = 12V, TA = 25C, VID4 = 1.
20
Additional Application Circuits
CS5166
+5V
MBRS120
MBRS120 MBRS120
1F
1200uF/10V x3
1F VCC VID0 VID1 VID2 VID3 VID4 COFF SS COMP 0.1F CS5166 VGATEL PGND ISENSE PWRGD VFB LGND 1000pF 0.1F VID4 VID3 VID2 VID1 VID0 0.1F IRL3103S 510 3.3K PWRGD PENTIUM(R)II SYSTEM 1200F/10V x5 IRL3103S 1.2H Droop Resistor (Embedded PCB trace) 3m Vcc Vss
VGATEH
330pF
Figure 35: +5V to +2.8V @ 14.2A for 300 MHz Pentium(R)II.
21
CS5166
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
D Lead Count 16L SO Wide Metric Max Min 10.50 10.10 English Max Min .413 .398
Thermal Data RJC RJA typ typ
16L SO Wide 23 105 C/W C/W
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299) 7.40 (.291)
10.65 (.419) 10.00 (.394)
0.51 (.020) 0.33 (.013)
1.27 (.050) BSC
2.49 (.098) 2.24 (.088)
2.65 (.104) 2.35 (.093)
1.27 (.050) 0.40 (.016)
REF: JEDEC MS-013
0.32 (.013) 0.23 (.009) D 0.30 (.012) 0.10 (.004)
Ordering Information
Part Number CS5166GDW16 CS5166GDWR16
Rev. 6/28/99
Description 16L SO Wide 16L SO Wide (tape & reel) 22
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
(c) 1999 Cherry Semiconductor Corporation

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